1. Field of the Invention
The present invention relates generally to the field of semiconductor packaging. More particularly, the present invention relates to a wafer level package and a method for manufacturing the same.
2. Description of the Prior Art
Semiconductor technologies are developing very fast, and especially semiconductor dies that require a tendency toward miniaturization. However, the requirements for the functions of the semiconductor dies preclude variety. Namely, the semiconductor dies must have more I/O pads in a smaller area, so the density of the pins is raised quickly. It causes the packaging for the semiconductor dies to become more difficult.
As known in the art, the process of wafer level packaging (WLP) packages the dies on a wafer before dividing the dies into respective dies. The WLP technology has some advantages, such as a shorter production cycle time and lower cost. Fan-out wafer-level packaging (FOWLP) is a packaging process in which contacts of a semiconductor die are redistributed over a larger area through a redistribution layer (RDL) that is typically formed on a substrate, such as a TSV interposer.
The RDL is typically defined by the addition of metal and dielectric layers onto the surface of the wafer to re-route the I/O layout into a looser pitch footprint. Such redistribution requires thin film polymers such as benzocyclobutene (BCB), polyimide (PI) or other organic polymers and metallization such as Al or Cu to reroute the peripheral pads to an area array configuration.
In wafer level packaging, the wafer and the dies mounted on the wafer are typically covered with a relatively thick layer of molding compound. Current fabrication process of the wafer level packaging includes thermal processes after molding. However, these post-molding thermal processes may increase the risk of known-good-die loss.